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E2U0062-18-84
Semiconductor ML7000-01/02/03 ML7001-01/02/03
Semiconductor Single Rail CODEC
This version: Aug. 1998 ML7000-01/02/03/ML7001-01/02/03
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GENERAL DESCRIPTION
The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the devices are optimized for ISDN terminals, digital wireless systems, and digital PBXs. The devices use the same transmission clocks as those used in the MSM7507. With the differential analog signal outputs which can drive 60 W load, the devices can directly drive a handset receiver.
FEATURES
* Single power supply: +5 V (ML7000-xx) +3 V (ML7001-xx) * Low power consumption Operating mode: 25 mW Typ. VDD = 5.0 V (ML7000-xx) 20 mW Typ. VDD = 3.0 V (ML7001-xx) Power-down mode: 0.05 mW Typ. VDD = 5.0 V (ML7000-xx) 0.03 mW Typ. VDD = 3.0 V (ML7001-xx) * Conforms to ITU-T Companding law ML7000-01/ML7001-01: m/A-law pin selectable ML7000-02/ML7001-02: m-law ML7000-03/ML7001-03: A-law * Transmission characteristics conform to ITU-T G.714 * Short frame sync timing operation * Built-in PLL eliminates a master clock * Serial data rate: 64/96/128/192/200/256/384/512/ 768/1024/1536/1544/2048 kHz * Adjustable transmit gain * Adjustable receive gain * Built-in reference voltage supply * Package options: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML7000-01MA/ML7001-01MA) (Product name: ML7000-02MA/ML7001-02MA) (Product name: ML7000-03MA/ML7001-03MA) 20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB) (Product name: ML7000-02MB/ML7001-02MB) (Product name: ML7000-03MB/ML7001-03MB)
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
BLOCK DIAGRAM
AIN- AIN+ GSX
- +
RC LPF
8th BPF
A/D CONV. AUTO ZERO
PCMOUT TCONT
PLL
XSYNC BCLK
SGC SG
SG GEN
VR GEN
RTIM
RSYNC (ALAW)
VFRO PWI AOUT-
- +
5th LPF
D/A CONV. RCONT
PCMIN
- + PWD - + PWD Logic PDN VDD AG DG
AOUT+
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1 AOUT+ 2 AOUT- 3 NC 4 PWI 5 VFRO 6 NC 7 VDD 8 DG 9
PDN 10 RSYNC 11 PCMIN 12
* The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/ ML7001-01MB. NC : No connect pin

24 SGC SG 1 20 SGC 23 AIN+ 22 AIN- 21 GSX 20 NC AOUT+ 2 AOUT- 3 PWI 4 19 AIN+ 18 AIN- 17 GSX 16 NC VFRO 5 VDD 6 DG 7 19 NC 15 (ALAW)* 14 AG 18 (ALAW)* 17 NC PDN 8 13 BCLK 16 AG RSYNC 9 12 XSYNC 15 BCLK PCMIN 10 11 PCMOUT 14 XSYNC 13 PCMOUT 20-Pin Plastic SSOP 24-Pin Plastic SOP
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PIN FUNCTIONAL DESCRIPTION
AIN+, AIN-, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN- is an inverting input to the op-amp; GSX is connected to the output of the op-amp. The level adjustment should be performed using any of the methods shown below. During power-saving and power-down modes, the GSX output is at AG voltage.
C1 Analog input R1
R2
GSX AIN- AIN+ SG
- +
R1 : variable R2 > 20 kW C1 > 1/(2 3.14 30 R1)
C2 Analog input R5 R4 R3
AIN+ AIN- GSX SG
+ -
R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 3.14 30 R5)
AG Analog ground. VFRO Receive filter output. The output signal has an amplitude of 2.4 VPP for ML7000-xx and 2.0 VPP for ML7001-xx above and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more. For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO and PWI. During power-saving or power-down mode, the VFRO output is at an SG level. When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency Characteristics Adjustment Circuit.
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Semiconductor PWI, AOUT+, AOUT-
ML7000-01/02/03/ML7001-01/02/03
PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT- pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT-. During power-saving or power down-mode, the outputs of AOUT+ and AOUT- are in a high impedance state. The output of AOUT+ is inverted with respect to the output of AOUT-. Since these outputs provide differential drive of an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric earphone or a line transformer. Refer to the application example.
VI VFRO PWI SG 20 kW SG - + AOUT- 20 kW - + AOUT+ VO ZL R6 R7 R6 > 20 kW ZL > 1.2 kW
Receive filter
Gain = VO/VI = 2 5 R7/R6 2
VDD Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx) PCMIN PCM data input. A serial PCM data input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of PCM is equal to the frequency of the BCLK signal. PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLK Shift clock signal input for the PCMIN and PCMOUT signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.
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Semiconductor RSYNC
ML7000-01/02/03/ML7001-01/02/03
Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.
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Semiconductor DG
ML7000-01/02/03/ML7001-01/02/03
Ground for the digital signal circuits. This ground is separate from the analog signal ground AG. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground AG. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from MSD in a sequential order. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down mode. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the even bits.
PCMIN/PCMOUT Input/Output Level MSD 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ML7000-02 (m-law) ML7001-02 (m-law) +Full scale +0 -0 -Full scale LSD 0 1 1 0 MSD 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 ML7000-03 (A-law) ML7001-03 (A-law) LSD 0 1 1 0
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Semiconductor SG
ML7000-01/02/03/ML7001-01/02/03
Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is 300 mA for ML7000-xx and 200 mA for ML7001-xx. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power-saving or power-down mode. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB have this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally pulled down.
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Symbol VDD VAIN VDIN Condition -- -- -- Rating -0.3 to +7 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Unit V V V
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Symbol VDD Ta VAIN VIH VIL Condition -- -- Connect AIN- and GSX Min. 4.75 2.70 -30 -- -- 2.2 XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW 0.45VDD 0 0 BCLK Typ. 5.00 3.00 +25 -- -- -- -- -- -- Max. 5.25 3.30 +85 2.4 1.2 VDD VDD 0.8 0.16VDD Unit V C VPP V V
64, 96, 128, 192, 200, 256, Clock Frequency FC 384, 512, 768, 1024, 1536, 1544, 2048 Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time XSYNC Setup Time XSYNC Hold Time Receive Sync Pulse Setting Time RSYNC Setup Time RSYNC Hold Time PCMIN Setup Time PCMIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width FS DC tlr tlf tCX tXC tXS tXH tCR tRC tRS tRH tDS tDH RDL CDL Voff -- XSYNC, RSYNC (-40 to +75 C) BCLK XSYNC, RSYNC, BCLK, PCMIN, PDN BCLKAEXSYNC, See Fig. 1 XSYNCAEBCLK, See Fig. 1 -- -- BCLKAERSYNC, See Fig. 1 RSYNCAEBCLK, See Fig. 1 -- -- -- -- Pull-up resistor -- Transmit gain stage, Gain = 0 dB Transmit gain stage, Gain = +20 dB XSYNC, RSYNC, BCLK 6.0 6.0 40 -- -- 50 50 50 50 50 50 50 50 50 50 0.5 -- -10 -100 -- 8.0 8.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9.0 10.0 60 50 50 -- -- -- -- -- -- -- -- -- -- -- 100 +10 +100 1000 kHz % ns ns ns ns ns ns ns ns ns ns ns ns kW pF mV mV ns kHz
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx. 9/19
Semiconductor
ML7000-01/02/03/ML7001-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: VDD = +5.0 V 5%, Ta = -30 to +85C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIH2 IIL VOL IO CIN ALAW -- Pull-up resistor = 500 W -- -- No signal XSYNC AE OFF Power-down mode, PDN = 0, BCLK OFF -- -- -- Condition Operating mode VDD = 5.0 V VDD = 3.0 V Min. -- -- -- -- -- 2.2 0.45VDD 0.0 0.0 -- -- -- 0.0 -- -- Typ. 5.0 6.5 1.5 2.0 0.01 -- -- -- -- -- -- -- 0.2 -- 5 Max. 12.0 10.0 4.0 8.0 0.05 VDD VDD 0.8 0.16VDD 2.0 30.0 0.5 0.4 10 -- Unit mA mA mA V V mA mA mA V mA pF
Power-saving mode, PDN = 1,
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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Semiconductor Transmit Analog Interface Characteristics
ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: VDD = +5.0 V 5%, Ta = -30 to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Gain = 1 Condition AIN+, AIN- GSX with respect to SG Min. 10 20 -- -1.2 -0.7 -20 Typ. -- -- -- -- -- -- Max. -- -- 30 +1.2 +0.7 +20 Unit MW kW pF V0p mV
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
Receive Analog Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: VDD = +5.0 V 5%, Ta = -30 to +85C) Parameter Input Resistance Output Load Resistance Symbol RINPW PWI RLVF RLAO CLVF CLAO VOVF Output Amplitude VOAO VFRO with respect to SG AOUT+, AOUT- (each) with respect to SG VFRO AOUT+, AOUT- VFRO, RL = 20 kW with respect to SG AOUT+, AOUT-, RL = 0.6 kW with respect to SG AOUT+, AOUT-, Gain = 1 with respect to SG Condition Min. 10 20 0.6 -- -- -1.2 -1.0 -1.3 -1.0 -100 -100 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 30 50 +1.2 +1.0 +1.3 +1.0 +100 +100 mV mV V0p Unit MW kW kW pF pF
Output Load Capacitance
VOSVF VFRO with respect to SG Offset Voltage VOSAO
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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Semiconductor AC Characteristics
ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: FS = 8 kHz, VDD = +5.0 V 5%, Ta = -30 to +85C) Symbol Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 -30 1020 SD T4 SD T5 SD R1 SD R2 SD R3 -40 -45 3 0 -30 1020 SD R4 SD R5 GT T1 GT T2 -40 -45 3 -10 1020 -40 -50 -55 3 -10 1020 -40 -50 -55 -0.3 -0.6 -1.2 -0.3 -0.6 -1.2 -0.3 *1 *1 0 -0.15 -0.15 0 35 35 35.0 34.0 26.0 26.0 24.0 -- 36 36 36.0 35.0 25.0 26.0 25.0 -- -0.3 0 Level Condition (dBm0) Min. 20 -0.15 -0.15 -0.15 0 -0.15 Typ. 26 +0.07 Reference -0.04 +0.07 0.4 -0.03 Reference 0.00 +0.05 0.54 43 41 38.0 38.0 31.0 30.0 25.0 25.0 43 41 40.0 40.0 32.0 32.0 27.0 27.0 +0.01 Reference -0.05 -0.05 -0.08 -0.06 Reference +0.08 +0.12 +0.15 +0.3 +0.6 +1.2 dB +0.3 +0.6 +1.2 +0.3 dB +0.2 +0.2 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +0.3 dB dB dB +0.2 +0.2 0.8 +0.2 Max. -- +0.2 dB Unit
Parameter
Transmit Frequency Response
Receive Frequency Response
Loss R3 Loss R4 Loss R5 SD T1 SD T2 SD T3
Transmit Signal to Distortion Ratio
Receive Signal to Distortion Ratio
Transmit Gain Tracking
GT T3 GT T4 GT T5 GT R1 GT R2
Receive Gain Tracking
GT R3 GT R4 GT R5
*1 Psophometric filter is used. Values above the dotted line are for ML7000-xx; those below, for ML7001-xx. 12/19
Semiconductor AC Characteristics (Continued)
ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: FS = 8 kHz, VDD = +5.0 V 5%, Ta = -30 to +85C) Freq. (Hz) -- -- Level Condition (dBm0) AIN = SG -- *1 *2 -- *1 *2 VDD = 5.0 V, Min. -- -- -- -- 0.58 0.338 0.58 0.483 *3 -0.2 -0.2 -- -- -- 0 *4 -- -- -- -- -- 0 *4 -- -- -- 0
TRANS AE RECV RECV AE TRANS
Parameter
Symbol Nidle T
Typ. -73.0 -69.5 -78.0 -75.0 0.6007 0.35 0.6007 0.5 -- -- -- 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 -85 -76
Max. -66.0 -65.0 -71.0 -65.0 0.622 0.362 0.622 0.518 0.2 0.2 0.6 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -75 -70
Unit
Idle Channel Noise Nidle R
dBm0p
AV T 1020 Absolute Level (Initial Difference) AV R Absolute Level 0
Ta = 25C VDD = 3.0 V, Ta = 25C *3
Vrms
AV Tt VDD = 5 V 5%, Ta = -30 to 85C A to A
(Deviation of Temperature and Power) AV Rt VDD = 2.7 to 3.3 V, Ta = -30 to 85C *3 Absolute Delay Td tGD T1 tGD T2 Transmit Group Delay tGD T3 tGD T4 tGD T5 tGD R1 tGD R2 Receive Group Delay tGD R3 tGD R4 tGD R5 Crosstalk Attenuation CR T CR R 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 0 BCLK = 64 kHz
dB
ms
ms
ms
-- --
dB
*1 *2 *3 *4
Psophometric filter is used. Input "0" code to PCMIN. AVR is defined at VFRO output. With respect to minimum value of the group delay distortion.
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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Semiconductor AC Characteristics (Continued)
ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = -30 to +85C) (ML7000-xx: FS = 8 kHz, VDD = +5.0 V 5%, Ta = -30 to +85C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Digital Output Delay Time Symbol Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz S IMD PSR T PSR R tXD1 tXD2 300 to 3400 fa = 470 fd = 320 0 to 50 kHz 0 -4 50 mVPP 4.6 kHz to 100 kHz 2fa - fb Measured inband *5 Min. 30 -- -- -- 20 20 Typ. 32 -37.5 -52 30 -- -- Max. -- -35 -35 -- 200 200 Unit dB dBm0 dBm0 dB ns
CL = 100 pF + 1 LSTTL Pull-up resistor = 500 W
*5 Measured under idle channel noise.
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing BCLK tXS tXH XSYNC tCX tXC tXD1 PCMOUT
MSD
1
2
3
4
5
6
7
8
9
10
11
12
tXD2 D2 D3 D4 D5 D6 D7 D8
Receive Timing BCLK tRS tRH RSYNC tCR tRC tDS PCMIN
MSD
1
2
3
4
5
6
7
8
9
10
11
12
tDH
D4 D5 D6 D7 D8
D2
D3
Figure 1 Basic Timing
15/19
Semiconductor
ML7000-01/02/03/ML7001-01/02/03
APPLICATION CIRCUIT
+ 5V ML7000-01 AIN- 600:600 600 W GSX AIN+ 600:600 300 W 300 W SG AOUT+ ALAW AOUT- PWI VFRO 51 kW 0.1 mF 10 mF 0V
+
1 kW PCM signal output 8 kHz SYNC signal input
0.1 mF 51 kW
PCMOUT XSYNC RSYNC BCLK PCMIN
PCM shift clock input PCM signal input Control of companding law 1: A-law 0: m-law
SGC DG AG 1 mF VDD
PDN
Power down control input 1: Normal operation 0: Power down
+5 V
0 to 20 W
+3 V ML7001-01 AIN- 600:600 600 W GSX AIN+ 600:600 300 W 300 W SG AOUT+ ALAW AOUT- PWI VFRO 51 kW 0.1 mF 10 mF 0V
+
1 kW PCM signal output 8 kHz SYNC signal input
0.1 mF 51 kW
PCMOUT XSYNC RSYNC BCLK PCMIN
PCM shift clock input PCM signal input Control of companding law 1: A-law 0: m-law
SGC DG AG 1 mF VDD
PDN
Power down control input 1: Normal operation 0: Power down
+3 V
0 to 20 W
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
NOTES ON USE
* To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin as closely as possible. Connect to the system ground with low impedance. * Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. * When mounted on a frame, use electromagnetic shielding if any electromagnetic wave sources such as power supply transformers surrounds the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
17/19
Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
ML7000-01/02/03/ML7001-01/02/03
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.18 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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